1. Sinha S, Swaminathan H, Kadamati G, Duvvury C. An automated tool for detecting ESD design errors. In: EOS/ESD Sympos, 1998. p. 208–17
2. Vassilev V, Lorenzini M, Groeseneken G, Steyaert M, Maes H. Analysis and improved compact modeling of the breakdown behavior of sub-0.25 micron ESD protection ggNMOS devices. In: EOS/ESD, 2001. p. 62–70
3. Wolf H, Gieser H, Stadler W, Esmark K. ESD circuit simulation for the prevention of ESD failures––application to products in a 0.18 um CMOS technology. In: IRPS, 2002. p. 162–70
4. Beebe S. Simulation of complete CMOS I/O circuit response to CDM stress. In: EOS/ESD Sympos, 1998. p. 259–70
5. Joshi S, Rosenbaum E. Compact modeling of vertical ESD protection NPN transistors for RF circuits. In: EOS/ESD-Sympos, 2002, p. 289–95