A write bit-line free sub-threshold SRAM cell with fully half-select free feature and high reliability for ultra-low power applications
Author:
Publisher
Elsevier BV
Subject
Electrical and Electronic Engineering
Reference43 articles.
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1. Design and Analysis of a Power-Efficient Dynamic Comparator with an Improved Transconductance in Ultra-low Power SAR ADC Applications;Circuits, Systems, and Signal Processing;2024-08-13
2. A FinFET-based low-power, stable 8T SRAM cell with high yield;AEU - International Journal of Electronics and Communications;2024-02
3. Energy-Efficient Single-Ended Read/Write 10T Near-Threshold SRAM;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-05
4. Single-sided gate-wrap-around CNTFET SRAM cell for utilization in reliable IoT-based platforms;AEU - International Journal of Electronics and Communications;2023-05
5. A 40nm 0.35V 25MHz Half-Select Disturb-Free Bitinterleaving 10T SRAM With Data-Aware Write-Path;2023 IEEE Custom Integrated Circuits Conference (CICC);2023-04
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