A 40nm 0.35V 25MHz Half-Select Disturb-Free Bitinterleaving 10T SRAM With Data-Aware Write-Path
Author:
Affiliation:
1. ShanghaiTech University,Shanghai,China
2. University of Southern California, LA,USA
Funder
National Natural Science Foundation of China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10121189/10121178/10121235.pdf?arnumber=10121235
Reference5 articles.
1. 40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist
2. A write bit-line free sub-threshold SRAM cell with fully half-select free feature and high reliability for ultra-low power applications
3. A Half-Select Disturb-Free 11T SRAM Cell With Built-In Write/Read-Assist Scheme for Ultralow-Voltage Operations
4. An Ultra-Low-Voltage Bit-Interleaved Synthesizable 13T SRAM Circuit
5. Half-Select Free and Bit-Line Sharing 9T SRAM for Reliable Supply Voltage Scaling
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