A 16-bit 2.5-MS/s SAR ADC with on-chip foreground calibration-Reference-Cited by-同舟云学术

A 16-bit 2.5-MS/s SAR ADC with on-chip foreground calibration

Published:2022-12 Issue: Volume:130 Page:105618
ISSN:0026-2692
Container-title:Microelectronics Journal
language:en
Short-container-title:Microelectronics Journal

Author:

Zhang Xiao-Wei^ORCID,Qian Fu-Yue,Xi Jian-Xiong,Wang Tao,He Le-Nian

Funder

People's Government of Guangdong Province

Publisher

Elsevier BV

Subject

General Engineering

Reference34 articles.

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3. A 1-MHz-bandwidth gm-c-based quadrature bandpass sigma-delta modulator achieving- 153.7-dBFS/Hz NSD with background calibration;Zhang;IEEE Trans. Circuits Syst. I. Regul. Pap.,2018

4. A 14-bit 125 MS/s IF/RF sampling pipelined ADC with 100 dB SFDR and 50 fs jitter;Ali Ahmed;IEEE J. Solid-State Circuits,2006

5. A 14-bit 20-MS/s pipelined ADC with digital distortion calibration;Daito;IEEE J. Solid-State Circuits,2006

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2. A 105-dB SFDR 16-bit SAR ADC with a Window Capacitor Calibration Scheme;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

3. Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications;Engineering Research Express;2024-02-15

4. A 14-bit 1-MS/s SAR ADC with a segmented capacitor array and background mismatch calibration for IoT sensing applications;Microelectronics Journal;2023-11

5. A 14-Bit 1-Ms/S Sar Adc with a Segmented Capacitor Array and Background Mismatch Calibration for Iot Sensing Applications;2023