1. A 14b 180MS/s pipeline-SAR ADC with adaptive-region-selection technique and gain error calibration;Hao;IEEE Trans. Circuits Syst. II,2024
2. A 12-bit 100-MS/s pipelined-SAR ADC with PVT-insensitive and gain-folding dynamic amplifier;Liu;IEEE Trans. Circuits Syst. I. Regul. Pap.,2020
3. A 625kHz-BW, 79.3dB-SNDR second-order noise-shaping SAR ADC using high-efficiency error-feedback structure;Yi;IEEE Trans. Circuits Syst. II,2022
4. A reconfigurable 12-to-18-bit dynamic zoom ADC with pole-optimized technique;Liang;IEEE Trans. Circuits Syst. I. Regul. Pap.,2023
5. A time-domain reconfigurable second-order noise shaping ADC with single fan-out gated delay cells;Yu;IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,2023