A 14-bit 125 MS/s IF/RF Sampling Pipelined ADC With 100 dB SFDR and 50 fs Jitter-Reference-Cited by-同舟云学术

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A 14-bit 125 MS/s IF/RF Sampling Pipelined ADC With 100 dB SFDR and 50 fs Jitter

Published:2006-08 Issue:8 Volume:41 Page:1846-1855
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:en
Short-container-title:IEEE J. Solid-State Circuits

Author:

Ali A.M.A.,Dillon C.,Sneed R.,Morgan A.S.,Bardsley S.,Kornblum J.,Wu L.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/34772/01661760.pdf?arnumber=1661760

Cited by 95 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Analysis and Calibration of Bit Weights in SAR and Pipelined SAR ADCs Based on Code Distribution;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-06

2. A Low Power 16-bit 125MS/s Pipeline ADC with 100dB SFDR;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

3. Asynchronous Continuous Time Pipeline Analog-to-Digital Converter;2024 IEEE Radar Conference (RadarConf24);2024-05-06

4. A 3.3V 14-bit 125MS/s pipeline ADC with hybrid 1.8V/3.3V MOSFET technique in 0.18µm CMOS;IEICE Electronics Express;2024-04-10

5. A low power 16-bit 50 MS/s pipeline ADC with 104 dB SFDR in 0.18 μm CMOS;Microelectronics Journal;2024-04

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