A 14-bit 125 MS/s IF/RF Sampling Pipelined ADC With 100 dB SFDR and 50 fs Jitter-Reference-Cited by-同舟云学术

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A 14-bit 125 MS/s IF/RF Sampling Pipelined ADC With 100 dB SFDR and 50 fs Jitter

Published:2006-08 Issue:8 Volume:41 Page:1846-1855
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:en
Short-container-title:IEEE J. Solid-State Circuits

Author:

Ali A.M.A.,Dillon C.,Sneed R.,Morgan A.S.,Bardsley S.,Kornblum J.,Wu L.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/34772/01661760.pdf?arnumber=1661760

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5. An Input Buffer with 85dB SFDR for High-Speed Pipeline ADC;2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA);2022-10-28

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