A 3.3V 14-bit 125MS/s pipeline ADC with hybrid 1.8V/3.3V MOSFET technique in 0.18µm CMOS
Author:
Affiliation:
1. Institute of Integrated Circuits and Systems, University of Electronic Science and Technology of China
2. GigaChip Technology Company Limited
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Link
https://www.jstage.jst.go.jp/article/elex/21/7/21_21.20240038/_pdf
Reference30 articles.
1. [1] R. Sehgal, et al.: “A 13-mW 64-dB SNDR 280-MS/s pipelined ADC using linearized integrating amplifiers,” IEEE J. Solid-State Circuits 53 (2018) 1878 (DOI: 10.1109/JSSC.2018.2815654).
2. [2] Y. Park, et al.: “An 11-b 100-MS/s fully dynamic pipelined ADC using a high-linearity dynamic amplifier,” IEEE J. Solid-State Circuits 55 (2020) 2468 (DOI: 10.1109/JSSC.2020.2987684).
3. [3] T.B. Cho and P.R. Gray: “A 10b, 20Msample/s, 35mW pipeline A/D converter,” IEEE J. Solid-State Circuits 30 (1995) 166 (DOI: 10.1109/4.364429).
4. [4] S.H. Lewis: “Optimizing the stage resolution in pipelined, multistage, analog-to-digital converters for video-rate applications,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process. 39 (1992) 516 (DOI: 10.1109/82.168943).
5. [5] J. Lagos, et al.: “A 1-GS/s, 12-b, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers,” IEEE J. Solid-State Circuits 54 (2018) 646 (DOI: 10.1109/JSSC.2018.2889680).
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