A low-power ADPLL using feedback DCO quarterly disabled in time domain-Reference-Cited by-同舟云学术

A low-power ADPLL using feedback DCO quarterly disabled in time domain

Published:2008-05 Issue:5 Volume:39 Page:832-840
ISSN:0026-2692
Container-title:Microelectronics Journal
language:en
Short-container-title:Microelectronics Journal

Author:

Wang Chua-Chin,Huang Chi-Chun,Tseng Sheng-Lun

Publisher

Elsevier BV

Subject

General Engineering

Reference9 articles.

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2. R. Nonis, N.D. Dalt, P. Palestri, L. Selmi, Modeling, design and characterization of a new low jitter analog dual tuning lc-vco pll architecture, in: International Symposium on Circuits and Systems (ISCAS ’98), vol. 4, May 2005, pp. 23–26.

3. Modeling, design and characterization of a new low jitter analog dual tuning lc-vco pll architecture;Nonis;IEEE J. Solid-State Circuits,2005

4. A fast lock digital phase-locked-loop architecture for wireless applications;Fahim;IEEE Trans. Circuits Syst. II,2003

5. Design and analysis of a portable high-speed clock generator;Hsu;IEEE Trans. Circuits Syst. II,2001

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