Design of an All-Digital Phase-locked loop in a 130nm CMOS Process using open-source tools-Reference-Cited by-同舟云学术

登录注册会员服务联系我们

Design of an All-Digital Phase-locked loop in a 130nm CMOS Process using open-source tools

Published:2022-04-22 Issue: Volume: Page:
ISSN:
Container-title:2022 International Conference on Electronic Systems and Intelligent Computing (ICESIC)
language:
Short-container-title:

Author:

S Charaan¹,S Nalinkumar¹,P Elavarasan¹,P Prakash¹,P Kasthuri¹

Affiliation:

1. Anna University,MIT Campus,Department of Electronics Engineering,Chennai,India

Funder

Anna University

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9783220/9783472/09783599.pdf?arnumber=9783599

Reference15 articles.

1. A Novel FastLocking ADPLL Based on Bisection Method;xiaoying;Electronics,2021

2. Design and Implementation of an All Digital Phase Locked Loop using a Pulse Output Direct Digital Frequency Synthesizer;gothandaraman;Master's Thesis University of Tennessee,2004

3. Digital Phase-Locked Loop Design Using SN54/74LS297;SN54/74LS297 Datasheet,0

4. Designs of All Digital Phase Locked Loop

5. Design an All Digital PLL with Ripple Reduction Technique;singla;International Journal of Innovative Technology and Exploring Engineering (IJITEE),2019

同舟云学术

1.学者识别学者识别

2.学术分析学术分析

3.人才评估人才评估

"同舟云学术"是以全球学者为主线，采集、加工和组织学术论文而形成的新型学术文献查询和分析系统，可以对全球学者进行文献检索和人才价值评估。用户可以通过关注某些学科领域的顶尖人物而持续追踪该领域的学科进展和研究前沿。经过近期的数据扩容，当前同舟云学术共收录了国内外主流学术期刊6万余种，收集的期刊论文及会议论文总量共计约1.5亿篇，并以每天添加12000余篇中外论文的速度递增。我们也可以为用户提供个性化、定制化的学者数据。欢迎来电咨询！咨询电话：010-8811{复制后删除}0370

www.globalauthorid.com

TOP