Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture-Reference-Cited by-同舟云学术

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Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture

Published:2005-06 Issue:6 Volume:40 Page:1303-1309
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Nonis R.,Da Dalt N.,Palestri P.,Selmi L.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/30932/01435608.pdf?arnumber=1435608

Cited by 32 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. PFD-Assisted Sampling PLL With Seamless PFD-SPD Switching Scheme and Supply-Insensitive RO;IEEE Microwave and Wireless Technology Letters;2023-10

2. A Comparative Study of Ring VCO and LC-VCO: Design, Performance Analysis, and Future Trends;IEEE Access;2023

3. A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fsrms Integrated Jitter and −251.6 dB FoM;Sensors;2021-11-18

4. A 0.35-V 240-μW Fast-Lock and Low-Phase-Noise Frequency Synthesizer for Implantable Biomedical Applications;IEEE Transactions on Biomedical Circuits and Systems;2019-12

5. A 4 GHz phase locked loop design in 65 nm CMOS for the Jiangmen Underground Neutrino Observatory detector;Journal of Instrumentation;2018-02-07

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