Design of a low-power, high performance, 8×8bit multiplier using a Shannon-based adder cell

Author:

Senthilpari C.,Singh Ajay Kumar,Diwakar K.

Publisher

Elsevier BV

Subject

General Engineering

Reference36 articles.

1. A review of 0.18-μm full adder performances for tree structured arithmetic circuits;Chang;IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,2005

2. Analysis and comparison on full adder block in submicron technology;Alioto;IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,2002

3. Low-power circuits and technology for wireless digital systems;Kosonocky;IBM J. Res. Dev.,2003

4. Reducing power by optimizing the necessary precision/range of floating-point arithmetic;Ying;IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,2000

5. Number-splitting with shift-and-add decomposition for power and hardware optimization in linear DSP synthesis;Nguyen;IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,2000

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