An ultra-low power multiplier using multi-valued adiabatic logic in 65 nm CMOS process

Author:

Yuejun Zhang,Dailu Ding,Zhao Pan,Pengjun Wang,Qiaoyan Yu

Funder

National Natural Science Foundation of China

Zhejiang Provincial Natural Science Foundation of China

S&T Plan of Zhejiang Provincial Science and Technology Department

Ningbo Natural Science Foundation

Publisher

Elsevier BV

Subject

General Engineering

Reference20 articles.

1. An efficient charge recovery logic circuit;Moon;IEEE J. Solid State Circ.,1996

2. Synthesis of dual-rail adiabatic logic for low power security applications, IEEE Trans. CAD Integr;Morrison;Circ. Syst.,2014

3. DPA-secured quasi-adiabatic logic (SQAL) for low-power passive RFID tags employing s-boxes;Avital;IEEE Trans. Circ. Syst. I: Regul. Pap.,2015

4. One-dimensional adiabatic circuits with inherent charge recycling;Khorami;Electron. Lett.,2015

5. Very-large-scale integration implementation of a 16-bit clocked adiabatic logic logarithmic signal processor;Yemiscioglu;IET Comput. Digital Tech.,2015

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