Study of Adiabatic Logic-Based Combinational and Sequential Circuits for Low-Power Applications
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Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-99-0639-0_3
Reference122 articles.
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2. Agrawal A, Gupta TK, Dadoria AK (2017) Ultra low power adiabatic logic using diode connected DC biased PFAL logic. Adv Electr Electron Eng 15(1):46–54. https://doi.org/10.15598/aeee.v15i1.1974
3. Akhila C, Kumar GR (2018) Design of sub-threshold adiabatic logic based Johnson’s ring counter. J Emerg Technol Innov Res 5(9):284–293
4. Akshitha, Rajan N (2019a) Power reduction of half adder and half subtractor using different partial adiabatic logic styles. In: Proceedings of the international conference on intelligent sustainable systems, no. Iciss, pp 87–92. https://doi.org/10.1109/ISS1.2019.8908104
5. Akshitha, Rajan N (2019b) Power reduction of half adder and half subtractor using different partial adiabatic logic styles. In: Proceedings of the international conference on intelligent sustainable systems, pp 87–92. https://doi.org/10.1109/ISS1.2019.8908104
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