Low-power circuits and technology for wireless digital systems
Author:
Publisher
IBM
Subject
General Computer Science
Link
http://xplorestaging.ieee.org/ielx5/5288520/5388931/05388940.pdf?arnumber=5388940
Cited by 13 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A Robust and Power-Efficient SoC Implementation in 65 nm;Journal of Computer Science and Technology;2013-07
2. Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review;Journal of Computers;2009-10-01
3. Design of a low-power, high performance, 8×8bit multiplier using a Shannon-based adder cell;Microelectronics Journal;2008-05
4. Design in the Power-Limited Scaling Regime;IEEE Transactions on Electron Devices;2008-01
5. Ring Oscillator Based Test Structure for NBTI Analysis;2007 IEEE International Conference on Microelectronic Test Structures;2007-03
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