A Robust and Power-Efficient SoC Implementation in 65 nm-Reference-Cited by-同舟云学术

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A Robust and Power-Efficient SoC Implementation in 65 nm

Published:2013-07 Issue:4 Volume:28 Page:682-688
ISSN:1000-9000
Container-title:Journal of Computer Science and Technology
language:en
Short-container-title:J. Comput. Sci. Technol.

Author:

Xiao Bin,Zhang Yi-Fu,Gao Yan-Ping,Yang Liang,Wu Dong-Mei,Fan Bao-Xia

Publisher

Springer Science and Business Media LLC

Subject

Computational Theory and Mathematics,Computer Science Applications,Hardware and Architecture,Theoretical Computer Science,Software

Link

http://link.springer.com/content/pdf/10.1007/s11390-013-1368-7.pdf

Reference16 articles.

1. Borkar S, Karnik T, Narendra S, Tschanz J, Keshavarzi A, De V. Parameter variations and impact on circuits and micro-architecture. In Proc. the 40th Annual Design Automation Conference, Jun. 2003, pp.338-342.

2. Karnik T, Borkar S, De V. Sub-90 nm technologies: Challenges and opportunities for CAD. In Proc. the 2002 IEEE/ACM Int. Conf. Computer-Aided Design, Nov. 2002, pp.203-206.

3. Hu W, Wang R, Chen Y, Fan B, Zhong S, Gao X, Qi Z, Yang X. Godson-3B: A 1 GHz 40 W 8-core 128GFLOPS processor in 65 nm CMOS. In Digest of Technical Papers of 2011 Int. Solid-State Circuits Conference (ISSCC), Feb. 2011, pp.76-78.

4. Hu W, Wang J, Gao X, Chen Y, Liu Q, Li G. Godson-3: A scalable multicore RISC processor with X86 emulation. IEEE Micro, 2009, 29(2): 17–29.

5. Fan B, Yang L, Gao Z, Zhang F, Wang R. The implementation and design methodology of a quad-core version Godson-3 microprocessor. In Proc. the 52nd IEEE Int. Midwest Symp. Circuits and Systems, Aug. 2009, pp.1167-1170.

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