A digital-mixing-based method for timing skew estimation in time-interleaved ADCs
Author:
Funder
Fundamental Research Funds for the Central Universities
National Natural Science Foundation of China
Publisher
Elsevier BV
Subject
General Engineering
Reference16 articles.
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2. A 12-b, 650-MSps time-interleaved pipeline analog to digital converter with 1.5 GHz analog bandwidth for digital beam-forming systems;Nazari;Analog Integr. Circuits Signal Process.,2016
3. A 12-bit 200-MS/s pipelined A/D converter with sampling skew reduction technique;Nam;Microelectron. J.,2011
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5. A 12 bit 1.6GS/s BiCMOS 2×2 hierarchical time-interleaved pipeline ADC;El-Chammas;IEEE J. Solid State Circuits,2014
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2. An 18‐bit 1‐GS/s time interleaved analog‐to‐digital converter with timing skew calibration based on an adaptive genetic algorithm;International Journal of Circuit Theory and Applications;2023-06-11
3. Hierarchical parallel difference-equalization and channels regrouping based estimation of timing skew for time-interleaved ADCs;Microelectronics Journal;2022-10
4. A time-interleaved ADC calibration technique for spectrum monitoring applications;Microelectronics Journal;2022-05
5. An Approximate Timing-Mismatch Calibration Technique for Interleaved ADCs;2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS);2021-08-09
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