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Hierarchical parallel difference-equalization and channels regrouping based estimation of timing skew for time-interleaved ADCs

  • Published:2022-10 Issue: Volume:128 Page:105564
  • ISSN:0026-2692
  • Container-title:Microelectronics Journal
  • language:en
  • Short-container-title:Microelectronics Journal

Author:

Zhi He,Li Xin,Yan Jiayan,Zhang Lizhen,Yang Chun,Wu JianhuiORCID

Funder

National Natural Science Foundation of China

Publisher

Elsevier BV

Subject

General Engineering

Reference38 articles.

1. Time- and frequency-interleaving: distinctions and connections;Song;IEEE Trans. Signal Process.,2021

2. Blind equalization of time errors in a time-interleaved ADC system;Elbornsson;IEEE Trans. Signal Process.,2005

3. Time-interleaved analog-to-digital converters: status and future directions;Vogel,2006

4. A CMOS 15-bit 125-MS/s time-interleaved ADC with digital background calibration;Lee,2006

5. A 2GS/s 8b time-interleaved SAR ADC for millimeter-wave pulsed radar baseband SoC;Miki,2016
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