A high-speed and scalable XOR-XNOR-based hybrid full adder design-Reference-Cited by-同舟云学术

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A high-speed and scalable XOR-XNOR-based hybrid full adder design

Published:2021-07 Issue: Volume:93 Page:107200
ISSN:0045-7906
Container-title:Computers & Electrical Engineering
language:en
Short-container-title:Computers & Electrical Engineering

Author:

Hasan Mehedi,Hussain Md. Shahbaz,Hossain Mainul,Hasan Mohd.,Zaman Hasan U.,Islam Sharnali

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,General Computer Science,Control and Systems Engineering

Reference25 articles.

1. Circuit and physical design of zEnterpriseTM EC12 microprocessor chip and multi-chip module;Warnock;IEEE J Solid-State Circuits,2014

2. New energy-efficient hybrid wide-operand adder architecture;Zafarzadehpour;IET Circuits Devices Syst,2019

3. Fast bit-parallel binary multiplier based on type-1 pentanomials;Imana;IEEE Trans Comput,2018

4. Low-power logarithmic number system addition/subtraction and their impact on their digital filters;Kouretas;IEEE Trans Comput,2013

5. Two new low-power full adder based on majority-not gates;Navi;Microelectron J,2009

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