CMOS Implementation of a Piecewise Linear Activation Function Based Neuron Unit for Neural Network Accelerator-Reference-Cited by-同舟云学术

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CMOS Implementation of a Piecewise Linear Activation Function Based Neuron Unit for Neural Network Accelerator

Published:2024-03-15 Issue: Volume: Page:1-5
ISSN:
Container-title:2024 2nd International Conference on Device Intelligence, Computing and Communication Technologies (DICCT)
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Author:

Chakraborty Arindom¹,Hasan Mehedi¹,Hussain Md. Shahbaz²,Kandpal Jyoti³,Hasan Mohd.²,Zaman Hasan U.⁴

Affiliation:

1. University of Science and Technology Chittagong,Depertment of EEE,Chattogram,Bangladesh

2. Aligarh Muslim University,Depertment of Electronics Engineering,Aligarh,India

3. Graphic Era Hill University,Department of Electronics and Communication Engineering,Dehradun,India

4. Samsung Semiconductor Inc.,Design for Test Depertment,San Diego,California,USA

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10532774/10532776/10533157.pdf?arnumber=10533157

Reference28 articles.

1. Novel Analog Implementation of a Hyperbolic Tangent Neuron in Artificial Neural Networks

2. Power Efficient Design of High-Performance Convolutional Neural Networks Hardware Accelerator on FPGA: A Case Study With GoogLeNet

3. An Architecture to Accelerate Convolution in Deep Neural Networks

4. A Fast Spiking Neural Network Accelerator based on BP-STDP Algorithm and Weighted Neuron Model

5. An Overview of Energy-Efficient Hardware Accelerators for On-Device Deep-Neural-Network Training

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