Subthreshold slope degradation model for localized-charge-trapping based non-volatile memory devices-Reference-Cited by-同舟云学术

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Subthreshold slope degradation model for localized-charge-trapping based non-volatile memory devices

Published:2003-05 Issue:5 Volume:47 Page:937-941
ISSN:0038-1101
Container-title:Solid-State Electronics
language:en
Short-container-title:Solid-State Electronics

Author:

Shappir Assaf,Shacham-Diamand Yosi,Lusky Eli,Bloom Ilan,Eitan Boaz

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference8 articles.

1. Low level currents in insulated gate field effect transistors;Barron;Solid-State Electron.,1972

2. VLSI limitations from drain-induced barrier lowering;Troutman;IEEE J. Solid-State Circ.,1979

3. A novel flash memory with split gate source side injection and ONO charge storage stack (SPIN);Chen;VLSI Tech. Symp.,1997

4. NROM: A Novel cell localized trapping 2bit non-volatile memory cell;Eitan;IEEE Electron. Dev. Lett.,2000

5. Hot-electron injection into the oxide in n-channel MOS devices;Eitan;IEEE Trans. Electron. Dev.,1981

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1. Multi-level 2-bit/cell operation utilizing Hf-based metal/oxide/nitride/oxide/silicon nonvolatile memory with HfO2 and HfON tunneling layer;Japanese Journal of Applied Physics;2022-01-13

2. A Comprehensive Characterization Method for Lateral Profiling of Interface Traps and Trapped Charges in P-SONOS Cell Devices;IEEE Transactions on Device and Materials Reliability;2017-03

3. Influence of Electron and Hole Distribution on 2T SONOS Embedded NVM;JSTS:Journal of Semiconductor Technology and Science;2016-10-30

4. Study of charge loss mechanisms for nano-sized localized trapping SONOS memory devices;Solid-State Electronics;2014-01

5. Effect of Damage in Source and Drain on the Endurance of a 65-nm-Node NOR Flash Memory;IEEE Transactions on Electron Devices;2013-12

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