Test pattern generation using thermometer code counter in TPC technique for BIST implementation-Reference-Cited by-同舟云学术

Test pattern generation using thermometer code counter in TPC technique for BIST implementation

Published:2019-11 Issue: Volume:71 Page:102890
ISSN:0141-9331
Container-title:Microprocessors and Microsystems
language:en
Short-container-title:Microprocessors and Microsystems

Author:

Jamal K.,Chari K. Manjunatha,Srihari P.

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference27 articles.

1. Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity;Girard,1999

2. DS-LFSR: a BIST TPG for low switchingactivity;Wang;IEEE Trans. Comput.-Aided Design Integr. Circuits Syst.,2002

3. Low power BIST via non-linear hybrid cellular automata;Corno,2000

4. A modified clock scheme for a low power BIST test patterngenerator;Girard,2001

5. Low power/energy BIST scheme for datapaths;Gizopoulos,2000

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