Switch Controlled State Skipping Based Memory Efficient Test Pattern Generator for BIST Application-Reference-Cited by-同舟云学术

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Switch Controlled State Skipping Based Memory Efficient Test Pattern Generator for BIST Application

Published:2023-12-07 Issue: Volume:975 Page:1-4
ISSN:
Container-title:2023 Second International Conference on Advances in Computational Intelligence and Communication (ICACIC)
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Author:

Nagaraju S.¹,Hemantha G. Reddy²,Balasundaram Shanmugham³

Affiliation:

1. Srinivasa Ramanujan Institute of Technology,Department of Electronics and Communication Engineering,Anantapur,Andhra Pradesh,India

2. Madanapalle Institute of Technology and Science,Department of Electronics and Communication Engineering,Madanapalle,Andhra Pradesh,India

3. Dhanalakshmi Srinivasan University,School of Engineering and Technology,Department of Electronics and Communication Engineering,Tiruchirappalli,Tamil Nadu,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10434932/10434945/10435300.pdf?arnumber=10435300

Reference17 articles.

1. A BIST Implementation framework for supporting field testability and configurability in an automotive SOC;Dutta

2. Power Optimization of Linear Feedback Shift Register (LFSR) for Low Power BIST

3. LFSR-Reseeding Scheme Achieving Low-Power Dissipation During Test

4. On-chip sinusoidal signal generation with harmonic cancelation for analog and mixed-signal BIST applications

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