16-bit three operand adder of CS3A and HC3A
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Publisher
AIP Publishing
Link
http://aip.scitation.org/doi/pdf/10.1063/5.0164127
Reference18 articles.
1. High-Speed Area-Efficient VLSI Architecture of Three-Operand Binary Adder
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3. Teffi Francis, Tresa Joseph, Jobin K. Antony, “Modified MAC unit for low power high speed DSP applicationusing multiplier with bypassing technique and optimized adders,” 2013 Fourth International Conference on Computing, Communications and Networking Technologies (ICCCNT), (2013).
4. Jamal, K., Chari, K. M., & Srihari, P. (2019), Test Pattern Generation using Thermometer Code Counter in TPC Technique for BIST Implementation, Microprocessors and Microsystems, 102890.
5. S. Muthyala Sudhakar, K. P. Chidambaram, and E. E. Swartzlander, Hybrid Han-Carlson adder, in Proc. IEEE55th Int. Midwest Symp. Circuits Syst. (MWSCAS), Boise, ID, USA, (Aug. 2012), pp. 818–821.
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