Author:
Muthyala Sudhakar Sreenivaas,Chidambaram Kumar P.,Swartzlander Earl E.
Cited by
25 articles.
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1. Performance of Well-Organized VLSI Architecture for Three Operand Binary Adder;2024 IEEE 4th International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA);2024-05-17
2. DESIGN AND ANALYSIS OF NOVEL PARALLEL PREFIX ADDERS FOR VLSI CIRCUITS;Suranaree Journal of Science and Technology;2024-03-19
3. Approximate Three-Operand Binary Adder for Error-Resilient Applications;2023 IEEE International Symposium on Smart Electronic Systems (iSES);2023-12-18
4. A Novel High Computing Power Efficient VLSI Architectures of Three Operand Binary Adders;International Journal of Engineering and Advanced Technology;2023-06-30
5. VLSI Architectures of Three Operand Binary Adders;2023 International Conference on Advances in Electronics, Communication, Computing and Intelligent Information Systems (ICAECIS);2023-04-19