Author:
Francis Teffi,Joseph Tresa,Antony Jobin K.
Cited by
5 articles.
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1. Approximate Vedic Multiplier Architecture for Efficient CNN Acceleration on Embedded Devices;2024 IEEE 48th Annual Computers, Software, and Applications Conference (COMPSAC);2024-07-02
2. Design and implementation of low power and area efficient hybrid AHL multiplier;AIP Conference Proceedings;2024
3. 16-bit three operand adder of CS3A and HC3A;LOW RADIOACTIVITY TECHNIQUES 2022 (LRT 2022): Proceedings of the 8th International Workshop on Low Radioactivity Techniques;2023
4. Application of ameliorated Harris Hawks optimizer for designing of low-power signed floating-point MAC architecture;Neural Computing and Applications;2021-01-16
5. Design of Advanced Multiplier using 15-4 Compressor;International Journal of Advanced Research in Science, Communication and Technology;2019-08-30