Gate-All-Around FETs: Nanowire and Nanosheet Structure
Author:
Yoon Jun-Sik,Jeong Jinsu,Lee Seunghwan,Lee Junjong,Baek Rock-Hyun
Abstract
DC/AC performances of 3-nm-node gate-all-around (GAA) FETs having different widths and the number of channels (Nch) from 1 to 5 were investigated thoroughly using fully-calibrated TCAD. There are two types of GAAFETs: nanowire (NW) FETs having the same width (WNW) and thickness of the channels, and nanosheet (NS) FETs having wide width (WNS) but the fixed thickness of the channels as 5 nm. Compared to FinFETs, GAAFETs can maintain good short channel characteristics as the WNW is smaller than 9 nm but irrespective of the WNS. DC performances of the GAAFETs improve as the Nch increases but at decreasing rate because of the parasitic resistances at the source/drain epi. On the other hand, gate capacitances of the GAAFETs increase constantly as the Nch increases. Therefore, the GAAFETs have minimum RC delay at the Nch near 3. For low power applications, NWFETs outperform FinFETs and NSFETs due to their excellent short channel characteristics by 2-D structural confinement. For standard and high performance applications, NSFETs outperform FinFETs and NWFETs by showing superior DC performances arising from larger effective widths per footprint. Overall, GAAFETs are great candidates to substitute FinFETs in the 3-nm technology node for all the applications.
Reference35 articles.
1. Loubet N, Hook T, Montanini P, Yeung C.-W, Kanakasabapathy S, Guillorn M, Yamashita T, Zhang J, Miao X, Wang J, Young A, Chao R, Kang M, Liu Z, Fan S, Hamieh B, Sieg S, Mignot Y, Xu W, Seo S.-C, Yoo J, Mochizuki S, Sankarapandian M, Kwon O, Carr A, Greene A, Park Y, Frougier J, Galatage R, Bao R, Shearer J, Conti R, Song H, Lee D, Kong D, Xu Y, Arceo A, Bi Z, Xu P, Muthinti R, Li J, Wong R, Brown D, Oldiges P, Wu T, Gupta D, Lian S, Divakaruni R, Gow T, Labelle C, Lee S, Paruchuri V, Bu H, Khare M. Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET. In: Proceedings of 2017 Symposium on VLSI Technology, Kyoto, 2017, pp. T230-T231, DOI: 10.23919/VLSIT.2017.7998183. 2. Yoon J.-S, Rim T, Kim J, Meyyappan M, Baek C.-K, and Jeong Y.-H. Vertical gate-all-around junctionless nanowire transistors with asymmetric diameters and underlap lengths. Applied Physics Letters. 2014;105:102105-1-4. DOI: 10.1063/1.4895030. 3. Lee Y. M, Na M. H, Chu A, Young A, Hook T, Liebmann L, Nowak E. J, Baek S. H, Sengupta R, Trombley H, and Miao X. Accurate performance evaluation for the horizontal nanosheet standard-cell design space beyond 7nm technology. In: Proceedings of 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2017, pp. 29.3.1-29.3.4, DOI: 10.1109/IEDM.2017.8268474. 4. Barraud S, Lapras V, Previtali B, Samson M. P, Lacord J, Martinie S, Jaud M.-A, Athanasiou S, Triozon F, Rozeau O, Hartmann J. M, Vizioz C, Comboroure C, Andrieu F, Barbé J. C, Vinet M. Ernst T. Performance and design considerations for gate-all-around stacked-nanowires FETs. In: Proceedings of 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2017, pp. 29.2.1-29.2.4, DOI: 10.1109/IEDM.2017.8268473. 5. Yakimets D, Garcia Bardon M, Jang D, Schuddinck P, Sherazi Y, Weckx P, Miyaguchi K, Parvais B, Raghavan P, Spessot A, Verkest D, Mocuta A. Power aware FinFET and later nanosheet FET targeting for 3nm CMOS technology. In: Proceedings of 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2017, pp. 20.4.1-20.4.4, doi: 10.1109/IEDM.2017.8268429.
Cited by
4 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
|
|