Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology-Reference-Cited by-同舟云学术

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Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology

Published:2017-12 Issue: Volume: Page:
ISSN:
Container-title:2017 IEEE International Electron Devices Meeting (IEDM)
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Author:

Yakimets D.,Bardon M. Garcia,Jang D.,Schuddinck P.,Sherazi Y.,Weckx P.,Miyaguchi K.,Parvais B.,Raghavan P.,Spessot A.,Verkest D.,Mocuta A.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8255107/8268301/08268429.pdf?arnumber=8268429

Cited by 45 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Benchmarking of Multi-Bridge-Channel FETs Toward Analog and Mixed-Mode Circuit Applications;IEEE Access;2024

2. Vertically Stacked Nanosheet Number Optimization Strategy for Complementary FET (CFET) Scaling Beyond 2 nm;IEEE Transactions on Electron Devices;2023-12

3. Investigation of Thermal Performance on Conventional and Junctionless Nanosheet Field Effect Transistors;Advanced Ultra Low‐Power Semiconductor Devices;2023-10-27

4. Nanosheet Count Optimization Strategy of Complementary FET (CFET) Scaling Beyond 2 nm From Device to Circuit;2023 International Workshop on Advanced Patterning Solutions (IWAPS);2023-10-26

5. Memory-Based Computing for Energy-Efficient AI: Grand Challenges;2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC);2023-10-16

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