Power, performance, and area evaluation across 180nm-28nm technology nodes based on benchmark circuits-Reference-Cited by-同舟云学术

Power, performance, and area evaluation across 180nm-28nm technology nodes based on benchmark circuits

Published:2024-05-10 Issue:9 Volume:21 Page:20240194-20240194
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Yin Minghui¹²³,Li Zhiqiang¹²³,Zhang Weihua¹²³,Liu Hongwei¹²³,Zhou Huanhuan¹³,You Yunxia¹³,Wang Chen¹³

Affiliation:

1. Institute of Microelectronics of the Chinese Academy of Sciences

2. University of Chinese Academy of sciences

3. State Key Lab of Fabrication Technologies for Integrated Circuits

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Link

https://www.jstage.jst.go.jp/article/elex/21/9/21_21.20240194/_pdf

Reference33 articles.

1. [1] International Roadmap for Devices and Systems: IEEE IRDS^TM (2022 Edition) (2022) https://irds.ieee.org/editions/2022

2. [2] H.N. Khan, et al.: “Science and research policy at the end of Moore’s law,” Nature Electronics 1 (2018) 14 (DOI: 10.1038/s41928-017-0005-9).

3. [3] R. Chau, et al.: “Benchmarking nanotechnology for high-performance and low-power logic transistor applications,” IEEE Trans Nanotechnol. 4 (2005) 153 (DOI: 10.1109/TNANO.2004.842073).

4. [4] X. Jiang, et al.: “New assessment methodology based on energy-delay-yield cooptimization for nanoscale CMOS technology,” IEEE Trans. Electron Devices 62 (2015) 1746 (DOI: 10.1109/TED.2015.2396575).

5. [5] M. Badaroglu and J. Xu: “Interconnect-aware device targeting from PPA perspective,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (2016) 1 (DOI: 10.1145/2966986.2980068).