Device Modeling Based on Cost-Sensitive Densely Connected Deep Neural Networks-Reference-Cited by-同舟云学术

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Device Modeling Based on Cost-Sensitive Densely Connected Deep Neural Networks

Published:2024 Issue: Volume:12 Page:619-626
ISSN:2168-6734
Container-title:IEEE Journal of the Electron Devices Society
language:
Short-container-title:IEEE J. Electron Devices Soc.

Author:

Tang Xiaoying¹^ORCID,Li Zhiqiang¹^ORCID,Zeng Lang²^ORCID,Zhou Hongwei²^ORCID,Cheng Xiaoxu³,Yao Zhenjie¹^ORCID

Affiliation:

1. Key Laboratory of Fabrication Technologies for Integrated Circuits, Chinese Academy of Sciences, Beijing, China

2. MIIT Key Laboratory of Spintronics, School of Integrated Circuit Science and Engineering, Fert Beijing Institute, Beihang University, Beijing, China

3. Primarius Technologies Company Ltd., Shanghai, China

Funder

Strategic Priority Research Program of the Chinese Academy of Sciences

CAS Youth Interdisciplinary Team

National Natural Science Foundation of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx8/6245494/10416702/10643157.pdf?arnumber=10643157

Reference34 articles.

1. Cramming More Components Onto Integrated Circuits

2. Sub-10 nm gate-all-around CMOS nanowire transistors on bulk Si substrate;Li

3. A practical Si nanowire technology with nanowire-on-insulator structure for beyond 10nm logic technologies

4. High-Frequency Gate-All-Around Vertical InAs Nanowire MOSFETs on Si Substrates

5. Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

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