Exploring the Suitability of Stacking Devices in a Vertical Nanowire to Implement a CMOS Inverter
Author:
Affiliation:
1. Institute of Microelectronics of Barcelona (IMB-CNM, CSIC), Bellaterra, Spain
Funder
Ministerio de Ciencia e Innovación
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Link
http://xplorestaging.ieee.org/ielx7/7729/10368312/10538053.pdf?arnumber=10538053
Reference25 articles.
1. Variability Aware Simulation Based Design- Technology Cooptimization (DTCO) Flow in 14 nm FinFET/SRAM Cooptimization
2. A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size
3. Vertical nanowire InGaAs MOSFETs fabricated by a top-down approach
4. Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology
5. Lateral versus vertical gate-all-around FETs for beyond 7nm technologies
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