Performance and design considerations for gate-all-around stacked-NanoWires FETs-Reference-Cited by-同舟云学术

Performance and design considerations for gate-all-around stacked-NanoWires FETs

Published:2017-12 Issue: Volume: Page:
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Container-title:2017 IEEE International Electron Devices Meeting (IEDM)
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Author:

Barraud S.,Lapras V.,Previtali B.,Samson M. P.,Lacord J.,Martinie S.,Jaud M.-A.,Athanasiou S.,Triozon F.,Rozeau O.,Hartmann J. M.,Vizioz C.,Comboroure C.,Andrieu F.,Barbe J. C.,Vinet M.,Ernst T.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8255107/8268301/08268473.pdf?arnumber=8268473

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