Accurate performance evaluation for the horizontal nanosheet standard-cell design space beyond 7nm technology-Reference-Cited by-同舟云学术

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Accurate performance evaluation for the horizontal nanosheet standard-cell design space beyond 7nm technology

Published:2017-12 Issue: Volume: Page:
ISSN:
Container-title:2017 IEEE International Electron Devices Meeting (IEDM)
language:
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Author:

Lee Y. M.,Na M. H.,Chu A.,Young A.,Hook T.,Liebmann L.,Nowak E. J.,Baek S. H.,Sengupta R.,Trombley H.,Miao X.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8255107/8268301/08268474.pdf?arnumber=8268474

Cited by 20 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. Unveiling Thermal Cross Talk in 5nm Gate-All-Around Stacked Nanosheet FETs: A Machine Learning Perspective;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06

3. Design Technology Co-Optimization and Time-Efficient Verification for Enhanced Pin Accessibility in the Post-3-nm Node;IEEE Access;2024

4. A Perspective View of Silicon Based Classical to Non-Classical MOS Transistors and their Extension in Machine Learning;Silicon;2023-06-12

5. Analysis of quantum confinement in nanosheet FETs by using a quantum drift diffusion model;Electronics and Communications in Japan;2023-02-08

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