Design and analysis of gate all around stacked nanosheet-DRAM for future technology node

Abstract

Abstract This paper reports a stacked Dynamic random-access transistor (DRAM) memory structure that is based on gate all-around nanosheet access transistor. A TCAD study is done to compare nanosheet DRAM and conventional saddle fin recessed channel access transistor (SRCAT) in terms of DRAM electrical characteristics and its row hammer-induced leakage. The nanosheet DRAM shows superior characteristics in terms of current driving capability, speed, and refresh than SRCAT. The nanosheet DRAM also shows significantly lower hammer-induced failure as compared to SRCAT because the original leakage path from the cell to the neighboring cell gets blocked due to the nanosheet device structure. We also investigate the effect of spacer length on nanosheet DRAM characteristics and show that extended spacer length is favorable for having better DRAM characteristics due to the floating body effect. Our study demonstrates the potential, and advantages of nanosheet DRAM architecture compared to the conventional SRCAT DRAM.