Impact of Thermomechanical Stresses on Bumpless Chip in Stacked Wafer Structure-Reference-Cited by-同舟云学术

Impact of Thermomechanical Stresses on Bumpless Chip in Stacked Wafer Structure

Published:2013-05-01 Issue:5S3 Volume:52 Page:05FE01
ISSN:0021-4922
Container-title:Japanese Journal of Applied Physics
language:
Short-container-title:Jpn. J. Appl. Phys.

Author:

Mizushima Yoriko,Kitada Hideki,Uchibori Chihiro J.,Maeda Nobuhide,Kodama Shoichi,Kim Youngsuk,Fujimoto Koji,Yoshimi Seiichi,Nakamura Tomoji,Ohba Takayuki

Publisher

IOP Publishing

Subject

General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering

Reference21 articles.

1. Thinned wafer multi-stack 3DI technology

2. Diffusion Resistance of Low Temperature Chemical Vapor Deposition Dielectrics for Multiple Through Silicon Vias on Bumpless Wafer-on-Wafer Technology

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