Review of Bumpless Build Cube (BBCube) Using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI)

Author:

Ohba Takayuki,Sakui Koji,Sugatani Shinji,Ryoson Hiroyuki,Chujo Norio

Abstract

Bumpless Build Cube (BBCube) using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI) is discussed. Bumpless interconnects between wafers and between chips and wafers are a second-generation alternative to the use of micro-bumps for WOW and COW technologies. WOW and COW technologies for BBCube can be used for homogeneous and heterogeneous 3DI, respectively. Ultra-thinning of wafers down to 4 μm offers the advantage of a small form factor, not only in terms of the total volume of 3D ICs, but also the aspect ratio of Through-Silicon-Vias (TSVs). Bumpless interconnect technology can increase the number of TSVs per chip due to the finer TSV pitch and the lower impedance of bumpless TSV interconnects. In addition, high-density TSV interconnects with a short length provide the highest thermal dissipation from high-temperature devices such as CPUs and GPUs. This paper describes the process platform for BBCube WOW and COW technologies and BBCube DRAMs with high speed and low IO buffer power by enhancing parallelism and increasing yield by using a vertically replaceable memory block architecture, and also presents a comparison of thermal characteristics in 3D structures constructed with micro-bumps and BBCube.

Publisher

MDPI AG

Subject

Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering

Reference112 articles.

Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Development of Resins for Bumpless Interconnects and Wafer-On-Wafer (WOW) Integration;Journal of The Japan Institute of Electronics Packaging;2024-08-01

2. High-Performance Thermal and Electrical Characteristics of Via-Last (BBCube) Process in Multi-Layer 3D Integration;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28

3. Warpage Control Technology using 300 mm Waffle Wafer Evaluated by High-Precision FEM Analysis;2024 International Conference on Electronics Packaging (ICEP);2024-04-17

4. Minimizing die fracture in 3DIC die integration;Journal of Micro/Nanopatterning, Materials, and Metrology;2024-01-02

5. Precise Warpage Control Technology for 12-Inch Bumpless Via-Last Chip-on-Wafer (COW) by Finite Element Method (FEM);2023 18th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT);2023-10-25

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