Performance analysis of junctionless DG‐MOSFET‐based 6T‐SRAM with gate‐stack configuration
Author:
Affiliation:
1. School of VLSI Design & Embedded SystemNational Institute of TechnologyKurukshetra136119India
2. Department of Electronics & Communication EngineeringNational Institute of TechnologyKurukshetra136119India
Publisher
Institution of Engineering and Technology (IET)
Subject
Condensed Matter Physics,General Materials Science,Biomedical Engineering,Bioengineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/mnl.2017.0702
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3. Nanoscale FinFET Based SRAM Cell Design: Analysis of Performance Metric, Process Variation, Underlapped FinFET, and Temperature Effect
4. Analytical modeling for the estimation of leakage current and subthreshold swing factor of nanoscale double gate FinFET device
5. Analog/RF performance analysis of channel engineered high- K gate-stack based junctionless Trigate-FinFET
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