Design and Simulation of Bi-Layer Optimized High K- Dielectric Medium for N-Mosfet with Wild Horse Optimization to Improve Electrical Characteristics

Abstract

Electronic devices for advanced modern semiconductor based technology, mainly focus on the design regarding lighter, faster and more affordable solutions to meet the specifications of modern digital electronics. Some of the drawbacks for minimizing device size in MOSFET include gate insulator scaling, Short-Channel Effects (SCEs), shallow junction technology and off-state leakage current in MOSFET devices. In addition, the traditional SiO2 as a dielectric material contains restricted maximum capacitance as well as increased tunnel current leakage due to the thickness. Hence, a High-k dielectric is required to replace SiO2 to overcome the mentioned issues. In this model, the N-type MOSFET is designed based on the bi-layer high K-dielectric medium with optimized thickness according to the maximum capacitance and minimum threshold voltage, which are implemented on VLSI based applications such as 6 T SRAM for evaluating the performance. The drain current of HfO2, Al2O3 and HfO2+Si3N4 for 2.5 v drain voltage are 1.87 mA, 1.51 mA and 3.54 mA. Then, the read and write delay of the single and bi-layer MOSFET are 70.84 ps, 82.64 ps, 95.21 ps and 10.24 ps, 15.47 ps, 21.74 ps. Thus, the designed and simulated bi-layer optimized high k- dielectric medium for N-MOSFET with wild horse optimization performs better electrical characteristics than the single layer dielectric medium MOSFET.