Author:
Mishra Alok Kumar,Kumar Ajit,Vaithiyanathan D.,Kaur Baljit
Publisher
Springer Nature Singapore
Reference20 articles.
1. Ahn, S. Y., & Cho, K. (2014). Small-swing domino logic based on twist-connected transistors. Electronics Letters, 50(15), 1054–1056.
2. Aly, R. E., & Bayoumi, M. A. (2007). Low-power cache design using 7t sram cell. IEEE Transactions on Circuits and Systems II: Express Briefs, 54(4), 318–322.
3. Bhavnagarwala, A. J., Kosonocky, S., Radens, C., Chan, Y., Stawiasz, K., Srinivasan, U., Kowalczyk, S. P., & Ziegler, M. M. (2008). A sub-600-mv, fluctuation tolerant 65-nm cmos sram array with dynamic cell biasing. IEEE Journal of Solid-State Circuits, 43(4), 946–955.
4. Chen, W. H., Chen, C. F., Chen, Y. J., Chiu, H. Y., Shen, C. H., Shieh, J. M., Hsueh, F. K., Yang, C. C., Chen, B. Y., Huang, G. W., et al. (2018). A dual-split-controlled 4p2n 6t sram in monolithic 3d-ics with enhanced read speed and cell stability for iot applications. IEEE Electron Device Letters, 39(8), 1167–1170.
5. Dasgupta, S., et al. (2017). Compact analytical model to extract write static noise margin (wsnm) for sram cell at 45-nm and 65-nm nodes. IEEE Transactions on Semiconductor Manufacturing, 31(1), 136–143.