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Design of ternary logic gates and circuits using GNRFETs

  • Published:2020-10 Issue:7 Volume:14 Page:972-979
  • ISSN:1751-858X
  • Container-title:IET Circuits, Devices & Systems
  • language:en
  • Short-container-title:IET Circuits, Devices & Systems

Author:

Madhuri Badugu Divya1ORCID,Sunithamani Subramani1

Affiliation:

1. Electronics and Communication Engineering DepartmentKoneru Lakshmaiah Education FoundationGunturAndhra Pradesh522502India

Funder

Science and Engineering Research Board

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Control and Systems Engineering

Cited by 34 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A highly-efficient ternary-capable GNRFETs-based three-valued half adder circuit using unary operators;Materials Science and Engineering: B;2024-08

2. Tri-state GNRFET-based fast and energy-efficient ternary multiplier;AEU - International Journal of Electronics and Communications;2024-04

3. High-speed and power-efficient ternary logic designs using GNR transistors;e-Prime - Advances in Electrical Engineering, Electronics and Energy;2024-03

4. CNTFET-based digital arithmetic circuit designs in ternary logic with improved performance;e-Prime - Advances in Electrical Engineering, Electronics and Energy;2024-03

5. 21T Ternary Full Adder Based on Capacitive Threshold Logic and Carbon Nanotube FETs;IEEE Transactions on Nanotechnology;2024
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