21T Ternary Full Adder Based on Capacitive Threshold Logic and Carbon Nanotube FETs-Reference-Cited by-同舟云学术

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21T Ternary Full Adder Based on Capacitive Threshold Logic and Carbon Nanotube FETs

Published:2024 Issue: Volume:23 Page:338-345
ISSN:1536-125X
Container-title:IEEE Transactions on Nanotechnology
language:
Short-container-title:IEEE Trans. Nanotechnology

Author:

Hashemipour Marzieh¹^ORCID,Mirzaee Reza Faghih²^ORCID,Navi Keivan³^ORCID

Affiliation:

1. Department of Computer Engineering, Khatam University, Tehran, Iran

2. Department of Computer Engineering, Shahr-e-Qods Branch, Islamic Azad University, Tehran, Iran

3. Computer Science Department, California State Polytechnic University, Pomona, CA, USA

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/7729/10368312/10495214.pdf?arnumber=10495214

Reference42 articles.

1. Investigation of Pass Transistor Logic in a 12nm FinFET CMOS Technology

2. Fast and Energy Efficient CNFET Adders with CDM and Sensitivity Based Device-Circuit Co-Optimization

3. A Highly Reliable, Dynamic Logic-Based Hybrid MTJ/CMOS Magnetic Full Adder for High-Performance and Low-Power Application

4. A Carry Lookahead Adder Based on Hybrid CMOS-Memristor Logic Circuit

5. Review of Capacitive Threshold Gate Implementations

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