High-speed and power-efficient ternary logic designs using GNR transistors-Reference-Cited by-同舟云学术

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High-speed and power-efficient ternary logic designs using GNR transistors

Published:2024-03 Issue: Volume:7 Page:100439
ISSN:2772-6711
Container-title:e-Prime - Advances in Electrical Engineering, Electronics and Energy
language:en
Short-container-title:e-Prime - Advances in Electrical Engineering, Electronics and Energy

Author:

Mahesh Kuruva^ORCID,Shameem Syed^ORCID

Publisher

Elsevier BV

Reference29 articles.

1. Analysis of crosstalk effects for ternary logic MWCNT bundled through silicon vias;Basha;ECS J. Solid State Sci. Technol.,2023

2. A systematic method to design efficient ternary high performance CNTFET-based logic cells;Zarandi;IEEe Access.,2020

3. Novel ternary adder and multiplier designs without using decoders or encoders;Aljaam;IEEe Access.,2021

4. Design of a ternary memory cell using CNTFETs;Lin;IEEE Trans. Nanotechnol.,2012

5. Low-complexity multiternary digit multiplier design in CNTFET technology;Srinivasu;IEEE Trans. Circ. Syst. II: Express Briefs,2016

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Tri-state GNRFET-based fast and energy-efficient ternary multiplier;AEU - International Journal of Electronics and Communications;2024-04

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