PLDD/NHALO-assisted low-trigger SCR for high-voltage tolerant ESD protection in foundry CMOS process without extra mask
Author:
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://digital-library.theiet.org/content/journals/10.1049/el_20092723?crawler=true&mimetype=application/pdf
Reference6 articles.
1. An Improved Bidirectional SCR Structure for Low-Triggering ESD Protection Applications
2. A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS ICs
3. High Holding Voltage Cascoded LVTSCR Structures for 5.5-V Tolerant ESD Protection Clamps
4. An Unassisted, Low Trigger-, and High Holding-Voltage SCR (uSCR) for On-Chip ESD-Protection Applications
5. RC-SCR: very-low-voltage ESD protection circuit in plain CMOS
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1. Gate-Controlled LVTSCR for High-Voltage ESD Protections in Advanced CMOS Processes;IEEE Transactions on Electron Devices;2023-04
2. Robust and Latch-Up-Immune LVTSCR Device with an Embedded PMOSFET for ESD Protection in a 28-nm CMOS Process;Nanoscale Research Letters;2020-11-11
3. High-Holding-Voltage Silicon-Controlled Rectifier for ESD Applications;IEEE Electron Device Letters;2012-10
4. Complementation SCR for RF IC ESD protection;Electronics Letters;2010
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