Complementation SCR for RF IC ESD protection
Author:
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://digital-library.theiet.org/content/journals/10.1049/el.2010.2567?crawler=true&mimetype=application/pdf
Reference5 articles.
1. PLDD/NHALO-assisted low-trigger SCR for high-voltage tolerant ESD protection in foundry CMOS process without extra mask
2. Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI
3. Low-Capacitance SCR With Waffle Layout Structure for On-Chip ESD Protection in RF ICs
Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Power-Line-Triggered ESD Protection SCR for 0–20 GHz Applications in CMOS Technology;IEEE Transactions on Electron Devices;2023-12
2. Low-Capacitance SCR Structure for RF I/O Application;IEEE Transactions on Electromagnetic Compatibility;2013-04
3. Low-Capacitance Low-Voltage Triggered SCR ESD Clamp Using nMOS With Asymmetric Drain for RF ICs;IEEE Transactions on Microwave Theory and Techniques;2011-02
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