Unified compact model for junctionless multiple-gate FETs including source/drain extension regions
Author:
Publisher
IOP Publishing
Subject
Condensed Matter Physics,Mathematical Physics,Atomic and Molecular Physics, and Optics
Link
https://iopscience.iop.org/article/10.1088/1402-4896/abc19d/pdf
Reference19 articles.
1. Multiple-gate SOI MOSFETs
2. Multiple-gate SOI MOSFETs: device design guidelines
3. FINFET Device Junction Formation Challenges
4. Junctionless multigate field-effect transistor
5. Nanowire transistors without junctions
Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Impacts of quantum confinement effect on threshold voltage and drain-induced barrier lowering effect of junctionless surrounding-gate nanosheet NMOSFET including source/drain depletion regions;Microelectronics Journal;2024-10
2. Review—Recent Trends on Junction-Less Field Effect Transistors in Terms of Device Topology, Modeling, and Application;ECS Journal of Solid State Science and Technology;2023-03-01
3. 2-D Quantum Confined Threshold Voltage Shift Model for Asymmetric Short-Channel Junctionless Quadruple-Gate FETs;IEEE Transactions on Electron Devices;2021-11
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