2-D Quantum Confined Threshold Voltage Shift Model for Asymmetric Short-Channel Junctionless Quadruple-Gate FETs-Reference-Cited by-同舟云学术

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2-D Quantum Confined Threshold Voltage Shift Model for Asymmetric Short-Channel Junctionless Quadruple-Gate FETs

Published:2021-11 Issue:11 Volume:68 Page:5504-5510
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Bae Min Soo^ORCID,Yun Ilgu^ORCID

Funder

Institute of BioMed-IT, Energy-IT and Smart-IT Technology (BEST), a Brain Korea 21 Plus program, in Yonsei University

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/9583611/09465359.pdf?arnumber=9465359

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Impacts of quantum confinement effect on threshold voltage and drain-induced barrier lowering effect of junctionless surrounding-gate nanosheet NMOSFET including source/drain depletion regions;Microelectronics Journal;2024-10

2. Pragmatic Evaluation of Process Corners in ULP Subthreshold Circuits With Quantum Confinement Effects in Junctionless Nanowire Transistor;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-01

3. A TCAD simulation-based analysis of the asymmetrically designed channel effects on double gate-junctionless field-effect nanowire transistor;2023 4th International Conference on Computing and Communication Systems (I3CS);2023-03-16

4. Performance Analysis of Dual Material Graded Channel Cylindrical Gate All Around (DMGC CGAA) FET with Source/Drain Underlap;2022 IEEE International Symposium on Smart Electronic Systems (iSES);2022-12

5. Buried Metal Silicon-on-Insulator Junctionless Transistor for Low Power CMOS Logic Circuits;Silicon;2022-08-31

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