Review—Recent Trends on Junction-Less Field Effect Transistors in Terms of Device Topology, Modeling, and Application

Abstract

Junction less field effect transistor, also known as JLFET, is widely regarded as the most promising candidate that has the potential to replace the more conventional MOSFET used in IC technology at the present time. These FETs are less likely to have short channel effects (SCEs) than devices with junctions, as shown by their remarkable subthreshold swing and drain induced barrier lowering (DIBL). Due to its gate coupling, the Gate-All-Around (GAA) JLFET is a better contender to uphold Moore’s law than other existing sub-22 nm device architectures and regular JLFET, which allows more precise channel tuning. In GAA device structure, SCEs are minimized in comparison to junctionless at the same node technology. Among GAA and JLFET at the same technology node, the SCE is kept to a minimum in GAA. Until now, none of the manuscripts have provided a comprehensive review of the various JLFET structures and modeling techniques for the analysis of their various device parameters in a single place. From device evaluation and application to qualitative & quantitative parameter analysis studies likewise subthreshold swing value, DIBL and switching ratio, this manuscript provides comprehensive information on the various structures of Junctionless and Gate-Around JLFETs in one place. Furthermore, the manuscript provides a brief overview of various device modeling techniques of JLFETs for enhancing the device’s characteristics and its application in various semiconductor industries. This manuscript will provide researchers with an overview of how to design future generations JLFET structures with improved performance and modeling simplicity.