Effect of ENIG deposition on the failure mechanisms of thermomechanically loaded lead‐free 2nd level interconnections in LTCC/PWB assemblies

Abstract

PurposeThe purpose of this paper is to investigate the effect of electroless NiAu (ENIG) deposition on the failure mechanisms and characteristic lifetimes of three different non‐collapsible lead‐free 2nd level interconnections in low‐temperature co‐fired ceramic (LTCC)/printed wiring board (PWB) assemblies.Design/methodology/approachFive LTCC module/PWB assemblies were fabricated and exposed to a temperature cycling test over a −40 to 125°C temperature range. The characteristic lifetimes of these assemblies were determined using direct current resistance measurements. The failure mechanisms of the test assemblies were verified using X‐ray and scanning acoustic microscopy, optical microscopy with polarized light, scanning electron microscope (SEM)/energy dispersive spectroscopy and field emission‐SEM investigation.FindingsA stable intermetallic compound (IMC) layer is formed between the Ni deposit and solder matrix during reflow soldering. The layer thickness does not grow excessively and the interface between the layer and solder is practically free from Kirkendall voids after the thermal cycling test (TCT) over a temperature range of −40 to 125°C. The adhesion between the IMC layer and solder matrix is sufficient to prevent separation of this interface, resulting in intergranular (creep) or mixed transgranular/intergranular (fatigue/creep) failure within the solder matrix. However, the thermal fatigue endurance of the lead‐free solder has a major effect on the characteristic lifetime, not the deposit material of the solder land. Depending on the thickness of the LTCC substrate and the composition of the lead‐free solder alloy, characteristic lifetimes of over 2,000 cycles are achieved in the TCT.Originality/valueThe paper investigates in detail the advantages and disadvantages of ENIG deposition in LTCC/PWB assemblies with a large global thermal mismatch (ΔCTE≥10 ppm/°C), considering the design and manufacturing stages of the solder joint configuration and its performance under harsh accelerated test conditions.