Design and Simulation of Reliable Low Power CMOS Logic Gates
Author:
Affiliation:
1. School of Electronics & Communication Engineering, Shri Mata Vaishno Devi University, Katra 182320, India
Publisher
Informa UK Limited
Subject
Electrical and Electronic Engineering,Computer Science Applications,Theoretical Computer Science
Link
https://www.tandfonline.com/doi/pdf/10.1080/03772063.2020.1847700
Reference19 articles.
1. TECHNIQUES FOR LOW LEAKAGE NANOSCALE VLSI CIRCUITS: A COMPARATIVE STUDY
2. Low-power design techniques for scaled technologies
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4. Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits
5. Power dissipation analysis and optimization of deep submicron CMOS digital circuits
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