Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits

Author:

Butzen Paulo F.,da Rosa Leomar S.,Chiappetta Filho Erasmo J.D.,Reis André I.,Ribas Renato P.

Publisher

Elsevier BV

Subject

General Engineering

Reference24 articles.

1. Leakage current mechanisms and leakage reduction techniques in deep-submicron CMOS circuits;Roy;Proceedings of IEEE,2003

2. 2007 International Technology Roadmap for Semiconductors (ITRS). [Online]. Available: http://public.itrs.net.

3. Ultrathin high-К gate stacks for advanced CMOS devices;Gusev;IEDM Technical Digest,2001

4. Leakage power analysis and reduction: models, estimation and tools;Agarwal;IEE Proceedings—Computers and Digital Techniques,2005

5. Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18um CMOS;Narendra;IEEE Journal of Solid-State Circuits,2004

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