Affiliation:
1. School of Electronics & Communication Engineering, Shri Mata Vaishno Devi University, Katra, India
Abstract
Background:
The insatiable need for low-power and high-performance integrated
circuit (IC) results in the development of alternative options for metal oxide semiconductor field
effect transistor (MOSFET) in the ultra-nanoscale regime. The practical challenge of the device
scaling limits the use of MOSFET for future technology nodes. ICs are equipped with billions of
transistors whose size must be scaled while increasing performance. As the size of the transistor
shrinks for the new technology node, the control of the gate over the channel also reduces, leading
to sub-threshold leakage. The non-planar technology is the potential methodology to design
the ICs for the future technology nodes. The fin-shaped field effect transistor (FinFET) is the
most valuable non-planar technology. High sub-threshold slope, better short channel effect
(SCE) control, high current drive strength, low dopant-prompted variations, and decreased power
dissipation are the prominent features of FinFET technology.
Objective:
FinFET is an advanced version of MOSFET in terms of geometrical structure. Therefore,
in this review paper, the different geometrical structures, working operations, design challenges,
future aspects, and the different configurations of FinFETs are presented. The performance
of the different configurations of a 1-bit full adder is evaluated and compared.
Methods:
An overview of FinFET evolution from the planar MOSFET, along with its architecture
supported by the requisite equations, is presented in the paper. Besides this, it also gives an
insight into the circuit simulation using the FinFETs for the process voltage temperature (PVT)
variations, width quantization, design challenges, and the future of FinFETs. A comparative
study of FinFET-based 1-bit full adder using various techniques is done to compute and compare
the leakage power, delay, and power delay product (PDP).
Results:
The full adders using FinFETs show less leakage power and PDP. The AND-OR logicbased
hybrid full adder using FinFETs shows the least energy consumption per switching. Fin-
FET-based gate diffusion input adder shows a 74 % reduction in dynamic power compared to
the full adder using MOSFET technology. The low power FinFET-based full adder shows a
54.16 % reduction in leakage power compared to the MOSFET-based full adder. The results
signify the effect of multi-gates in curbing the leakage power dissipation.
Conclusion:
MOSFET faces the practical challenge of device scaling and SCEs at lower technology
nodes. It initiates the multi-gate technology for future system generation. FinFET has the
capability to design low-power and high-performance circuits in an ultra-nanoscale regime. The
geometrical structure of FinFET plays a key role to improve the performance metrics in an ultrananoscale
regime.
Publisher
Bentham Science Publishers Ltd.
Subject
Pharmaceutical Science,Biomedical Engineering,Medicine (miscellaneous),Bioengineering,Biotechnology
Cited by
11 articles.
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